Measurements made by high-speed oscilloscopes have suffered from time jitter caused by occurrences of metastable states in digital circuits. Time jitter occurs whenever an external signal being measured undergoes transitions from one state to another at times essentially coincident with internal oscilloscope signals undergoing transitions between logic states. This is true for external signals in either analog or digital form. Circuit designers have long known about such "race" conditions and have sought to avoid them by the use of synchronous circuit designs wherein all signals are derived from a common system clock, thereby eliminating coincidence of logic signal transitions.
Such "race" conditions can confuse logic circuits when, for example, two signals applied to different inputs of a flip-flop undergo nearly coincident changes between logic states and cause the output signal of the flip-flop to settle in an undefined state. The correct state often results, but the output signal may contain extraneous transitions until the circuit settles to its final logic state. It is also possible for the output signal to change to its final logic state following an unpredictable delay. Such unpredictable and untrustworthy signal states are called metastable states.
In measurement instruments such as oscilloscopes, it is impossible to ensure that externally applied signals being measured will be synchronous to the internal signals being used to make a measurement. A common example of such a pair of signals is the oscilloscope trigger and trigger hold-off signals. The trigger signal is commonly derived from an externally applied signal being measured and is, therefore, a completely arbitrary time-varying signal with unknown waveform characteristics. Once the oscilloscope is triggered, its internal circuitry generates various signals including the trigger hold-off signal. The trigger hold-off signal is used to prevent the generation of additional trigger signals until the current measurement being made is completed and the oscilloscope is ready to make another measurement. Time jitter may occur whenever the trigger hold-off signal changes logic states at about the same time a new trigger signal is received by the oscilloscope. The degree of coincidence that can cause time jitter is a time interval that can be determined from the known electrical characteristics of the logic circuits being driven by the trigger signal and trigger hold-off signal.
Previous art, such as dual synchronizer circuits, minimize the problem but do not eliminate trigger time jitter. The dual synchronizer circuit is used in a variety of oscilloscopes manufactured by Tektronix, Inc., Beaverton, Oreg., including its 11,000 series digital oscilloscopes.
FIG. 1, shows a prior art dual synchronizer circuit 8 that minimizes, but does not eliminate, metastable states in asynchronous logic circuits. Referring to FIG. 1, a hold-off signal and a trigger signal are applied to respectively a D (data) input 10 and a C (clock) input 12 of a first stage flip-flop 14. Whenever the trigger signal changes logic states in a positive-going direction, the signal logic state at D input 10 appears at Q output 16 of flip-flop 14. The signal at Q output 16 might be metastable if the trigger signal at input 12 changes logic stares in a positive-going direction at the same time that the hold-off signal at D input 10 changes logic states.
To minimize the possibility of metastable states, the D input of a second flip-flop 18 is coupled to Q output 16 of flip-flop 14. The clock input C of flip-flop 18 is coupled to the trigger signal through a time delay element 20. The time delay imparted to the trigger signal by delay element 20 exceeds the signal propagation delay through flip-flop 14. Delay element 20 can be implemented as a series of gates, a long piece of cable, or other means of delaying the propagation time of the trigger signal to the output 22 of delay element 20. The result is that flip-flop 18 receives as input signals the signal appearing on output 16 of flip-flop 14 and the delayed trigger pulses appearing on output 22 of delay element 20.
Dual synchronizer circuit 8 operates under the assumption that even if the signal on output 16 of flip-flop 14 is metastable, it will settle by the time delayed trigger signal output 22 of delay element 20 is applied to flip-flop 18. Therefore, the output 24 of second stage flip-flop 18 is assumed to be a reliable main hold-off signal. The problem with dual synchronizer 8 is that a small percentage of signals appearing on output 16 of first stage flip-flop 14 will take longer to settle than the delay imparted by delay element 20, or will settle to an incorrect logic state thereby rendering unreliable the signal on output 24 of second stage flip-flop 18.
A trigger resynchronization circuit described by Metz in U.S. Pat. No. 4,797,572 also minimizes but does not eliminate trigger time jitter. Metz describes a conventional trigger detecting circuit followed by delay and logic gate elements intended to eliminate all triggers except those in which the trigger signal and trigger hold-off signal are separated in time by an amount in excess of the delay element propagation time. The Metz circuit is another form of synchronizer circuit.
Trigger time jitter is particularly bothersome in high-speed digital sampling oscilloscopes because sampled measurement points may be stored and displayed at incorrect locations, thereby producing a cluttered display that remains until the entire display is cleared. Further, as oscilloscope measurement bandwidth increases, so does the need for increasing the triggering bandwidth, which must be equal to or greater than the measurement bandwidth. Increasing the triggering bandwidth increases susceptibility to time jitter-causing metastable conditions.
Thus, it has become more important to eliminate rather than just minimize metastable-caused time jitter conditions. Unfortunately, most circuit improvements that lead to reduced time jitter also ten to reduce the effective bandwidth of the logic circuits they are designed to protect from time jitter.